This invention relates generally to analog circuit architecture, and, more particularly to broadband transimpedance amplifiers for converting currents to voltages.
Current trends toward the integration of electro-optic interfaces with high-speed digital integrated circuits for local and/or storage area networks and other short-haul applications require low-voltage interface circuits that can operate from available digital supplies. In order to make arrays of these interconnects efficient and a feasible alternative to electrical interconnects in server and mainframe applications, low power consumption must be also achieved. (See A. Schild, et al., “Amplifier Array for 12 Parallel 10 Gb/s Optical-Fiber Links Fabricated in a SiGe Production Technology”, 2002 IEEE RFIC Symposium, pp. 89–92, 2002, incorporated herein by reference.) To avoid coding requirements for the transmitted data, a DC-coupled interface is desirable. To meet these requirements, new circuit topologies and approaches are required.
In optoelectronic communication systems, light is used to transmit data. A photodetector then converts the light signal to an electric current signal. This current signal must then be converted to a voltage signal and amplified to interface with typical digital systems. A transimpedance amplifier (TIA) is typically used for this task. (See H.-M. Rein and M. Moller “Design Considerations for Very-High-Speed Si-Bipolar IC's Operating up to 50 Gb/s”, IEEE Journal of Solid-State Circuits, vol. 31, No. 8, pp. 1076–1090, August 1996, incorporated herein by reference.)
Traditional TIA designs, such as shown in FIG. 1, typically use a voltage gain stage with a negative feedback resistance Rf 2 . This approach has some deficiencies for low-power, low-voltage systems at high data rates. The main problem with this approach is that, for correct operation, the input impedance of the voltage gain stage must be large. Thus, the feedback resistance Rf 2 and the voltage gain A 3 set the TIA input impedance. This means that the circuit's frequency response has a pole at the input node that is a function of the feedback resistance (which is approximately equal to the TIA's gain for large voltage gain (A)) and the photodiode capacitance, creating a gain-bandwidth trade-off.
Equivalent input noise is another crucial performance metric for any TIA, as it sets the sensitivity limit for the receiver. As feedback resistance Rf 2 decreases, to increase the frequency of the input pole for a fixed capacitance of a photodiode 4, the input noise increases. Therefore, a trade-off must be made in this TIA configuration between sensitivity/gain and bandwidth.
Further, the performance of such systems is limited by the performance of the voltage gain stage, which strongly effects the power consumption, the bandwidth and the required power supply voltage for the overall TIA.
Some CMOS designers have suggested using a common gate (CG) stage as a current buffer at the input, such as shown in FIG. 2. (See S. S. Mohan, T. H. Lee, “A 2.125 Gbaud 1.6 kΩ Transimpedance Preamplifier in 0.5 μm CMOS”, IEEE Custom Integrated Circuits Conference 1999, pp. 513–516, 1999.) This configuration presents an input impedance of 1/gm to the photodiode 4 and allows the feedback resistance Rf 2 to be increased, as its effect is now seen by a node with a smaller capacitance.
A concern with this configuration is that a bias current path for the CG stage must still be provided and the bias path input impedance RD 5 must be much greater than the feedback resistance Rf 2 so that the transimpedace gain is not impaired by the resulting current division. In this way, the feedback resistance is still limited by the maximum bias resistor Rb 6 value that can be used for the given power supply voltage and current requirements.
A further complication with this topology is finding a way to provide a proper bias for the CG stage over the wide range of input current levels that will be seen if the photodiode 4 is DC coupled to the TIA. This problem is amplified by the exponential response of the current to Vbe variations in a bipolar technology, which may make it difficult to sustain a constant collector current in a common base (CB) stage configuration with variations in DC photodiode current for a DC coupled system.
Another proposed TIA architecture uses a common-gate transistor terminated into a load and an error amplifier to adjust the common-gate operating point. That fairly complex architecture has a relatively high power consumption and larger chip area and may require the use of a higher voltage supply to accommodate the error amplifier. Furthermore, the input impedance and operating point of such a TIA remains a function of the signal applied to the input. Thus, it would be desirable to have a simplified TIA architecture that allows the TIA operating point to be independent of the input signal.
DC coupling is desirable for short-haul systems, as AC coupling may require data coding and coding results in undesired overhead (latency, power and chip area). Therefore the low frequency (LF) cut-off of the TIA must be as close to DC as possible to avoid baseline wander and ISI that would result from Fourier components of the signal falling below the LF cut-off. DC coupling can present problems in receivers due to variations in the DC input current with input signal power level affecting the bias conditions of the TIA. As such, a topology that is insensitive to these variations over a reasonable range of input power levels is desired.